Data and control pipelines are common in digital electronics. Earlier SDRAM controllers using a pipelined approach failed. Variable delays between different stages of SDRAM transactions proved to be extremely difficult to accommodate. The addition of page mode transactions was even worse. Page mode transactions skipped some stages entirely. Static random access memory (SRAM) transactions failed completely. The SRAM transactions used all the stages in parallel, instead of sequentially like the SDRAM transactions.
It would be desirable to have a SDRAM controller that accommodates SDRAM and SRAM transactions.